1. Field of the Invention
The present invention generally relates to a structure of a complementary metal oxide semiconductor field effect transistor, and more particularly, to a structure of a multi-gate metal oxide semiconductor field effect transistor (multi-gate MOSFET) and a manufacturing method thereof.
2. Description of the Prior Art
The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. Reduction in the size of MOSFETs has provided continued improvement in speed, performance, circuit density and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects.
Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-30 nm regime, approaches involving the use of multi-gate field-effect transistors (multi-gate FETs) are being investigated to improve the short channel effects. Generally, multi-gate FETs comprise raised source/drain regions having one or more raised channel regions, and a gate dielectric and a gate electrode are formed over the fin. It has been found that multi-gate FETs provide for improved scalability as design requirements shrink and better short-channel control.
It is difficult, however, to achieve a uniform three-dimensional implantation of the lightly doped drain (LDD), doped halo regions and source/drain regions. For example, according to a method disclosed in a prior art for fabricating tri-gate devices, even though two ion implantation processes with different tilt angles are carried out for forming a LDD region and/or a halo region at each end and/or at the bottom of the fin, the conformality of the LDD regions is still not good enough to meet the requirements in high-end products. Furthermore, corresponding external resistance (Rext) of the fin needs to be reduced as the size of the devices continuously shrinks. As a result, an improved multi-gate FET structure and method of fabricating a multi-gate FET are needed.